The publication by B. Eitan et al.: “NROM: A Novel Localized Trapping, 2-Bit NonVolatile Memory Cell” in IEEE Electron Device Letters 21, 543 to 545 (2000), describes a nonvolatile memory cell in which an oxide-nitride-oxide layer sequence is present as storage medium between the channel region and the gate electrode, which forms a part of the word line. This memory cell is programmed by “channel hot electron injection” and erased by “tunneling enhanced hot hole injection”. During programming, charge carriers are trapped in the nitride layer of the storage layer. This component has a storage capacity of 2 bits which are stored in each case at the junction between source and drain and the channel region.
This memory cell requires relatively high voltages at drain and gate for storage. This can lead to the so-called punch-through of the transistor if the latter is formed with a short channel length. The memory cells to date still have channel lengths of more than 250 nm; in this case, the occurrence of the punch-through is not as yet very pronounced.